`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:22:51 03/30/2014 
// Design Name: 
// Module Name:    Four 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Tone ( audio , sys_CLK , button, j);
 
	output    audio;
	input     sys_CLK, button;
	input	[2:0] j;
 
	reg  [23:0] counter4Hz, counter6MHz;
	reg  [13:0] count,origin;
	reg  audiof;
	reg  clk_6MHz, clk_4Hz;
	reg  [7:0]  len;
 
	assign audio= (button&&(origin!='d0))? audiof : 1'b1 ;  //????
 
	always @(posedge sys_CLK) begin        //6MHz??
		if(counter6MHz==4) begin
			counter6MHz=0;
			clk_6MHz=~clk_6MHz;
		end
		else begin
         counter6MHz=counter6MHz+24'b1;
		end
	end
 
	always @(posedge sys_CLK) begin        //4Hz??
		if(counter4Hz==1562500) begin
			counter4Hz=0;
         clk_4Hz=~clk_4Hz;
		end
		else begin
         counter4Hz=counter4Hz+24'b1;
		end
	end
 
	always @(posedge clk_6MHz) begin
		if(count==16383) begin
         count=origin;
         audiof=~audiof;
		end
		else begin
         count=count+14'b1;
		end
	end
 
	always @(posedge clk_4Hz)  begin
		case(j)
			'd0:origin='d4916;
			'd1:origin='d4916;  //low
			'd3:origin='d7281;
			'd5:origin='d8730;
			'd6:origin='d9565;
			default:origin='d0;
		endcase             
	end
	
endmodule
 